%0 Journal Article %1 InterCore %A Zhong, Rongrong %A Zhu, Yongxin %A Chen, Weiwei %A Lin, Mingliang %A Wong, Weng-Fai %C Los Alamitos, CA, USA %D 2007 %I IEEE Computer Society %J ainaw %K Communication InterCore ManyCore PhD Proposal Simulator %P 758-763 %R http://doi.ieeecomputersociety.org/10.1109/AINAW.2007.87 %T An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar %V 1 %X In the recent years, multi-core processors prove their extensive use in the area of System-on-Chip (SoC) on a single chip. This paper proposes a methodology and implements a multi-core simulator. The multi-core simulator is based on SimpleScalar integrated with SystemC framework, which deals with communication and synchronization among different processing modules. A shared memory scheme is introduced for inter-core communication with a set of shared memory access instructions and communicationmethods. A synchronization mechanism, which only switches the simulation component when communication occurs, is proposed for efficiency. Experiments prove that our simulator can correctly simulate the behavior of a multi-core system and demonstrate a high performance on Linux PC platforms. %@ 0-7695-2847-3

@article{InterCore, abstract = {In the recent years, multi-core processors prove their extensive use in the area of System-on-Chip (SoC) on a single chip. This paper proposes a methodology and implements a multi-core simulator. The multi-core simulator is based on SimpleScalar integrated with SystemC framework, which deals with communication and synchronization among different processing modules. A shared memory scheme is introduced for inter-core communication with a set of shared memory access instructions and communicationmethods. A synchronization mechanism, which only switches the simulation component when communication occurs, is proposed for efficiency. Experiments prove that our simulator can correctly simulate the behavior of a multi-core system and demonstrate a high performance on Linux PC platforms.}, added-at = {2008-08-16T21:46:08.000+0200}, address = {Los Alamitos, CA, USA}, author = {Zhong, Rongrong and Zhu, Yongxin and Chen, Weiwei and Lin, Mingliang and Wong, Weng-Fai}, biburl = {https://www.bibsonomy.org/bibtex/2cbdccd1f7ee44a84a758ddf48951e763/gron}, description = {An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar}, doi = {http://doi.ieeecomputersociety.org/10.1109/AINAW.2007.87}, interhash = {1c63fc25f98ed081e395980ae559e6ac}, intrahash = {cbdccd1f7ee44a84a758ddf48951e763}, isbn = {0-7695-2847-3}, journal = {ainaw}, keywords = {Communication InterCore ManyCore PhD Proposal Simulator}, pages = {758-763}, publisher = {IEEE Computer Society}, timestamp = {2008-08-16T21:46:08.000+0200}, title = {An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar}, volume = 1, year = 2007 }