Alternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA
B. Kathole. International Journal of Trend in Scientific Research and Development, 2 (3):
2542-2549(апреля 2018)
Аннотация
Contemporary ?eld-programmable gate array (FPGA) design requires a spectrum of available physical resources. As FPGA logic capacity has grown, locally accessed FPGA embedded memory blocks have increased in importance. When targeting FPGAs, application designers often specify high-level memory functions, which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this paper, a set of power efficient logical-to-physical RAM mapping algorithms is described, which converts user de?ned memory speci?cations to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-ef?cient choice. Our automated approach has been validated with both simulation of power dissipation and measurements of power dissipation on FPGA hardware. A comparison of measured power reductions to values determined via simulation con?rms the accuracy of our simulation approach. Our power-aware RAM mapping algorithms have been integrated into a commercial FPGA compiler and tested with 34 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 26% and overall core dynamic power can be reduced by 6% with a minimal loss (1%) in design performance. In addition, it is shown that the availability of multiple embedded memory block sizes in an FPGA reduces embedded memory dynamic power by an additional 9.6% by giving more choices to the computer-aided design algorithms. Bhagyashree Ashok Gavhane | Prashant Vitthalrao KatholeÄlternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3 , April 2018, URL: http://www.ijtsrd.com/papers/ijtsrd7172.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/7172/alternative-ram-mapping-algorithm-for-embedded-memory-blocks-in-fpga/bhagyashree-ashok-gavhane
%0 Journal Article
%1 noauthororeditor
%A Kathole, Bhagyashree Ashok Gavhane Prashant Vitthalrao
%D 2018
%J International Journal of Trend in Scientific Research and Development
%K & (FPGAs) ?eld-programmable Communication Electronics Engineering architecture arrays automation demand designing gate memory power
%N 3
%P 2542-2549
%T Alternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA
%U http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/7172/alternative-ram-mapping-algorithm-for-embedded-memory-blocks-in-fpga/bhagyashree-ashok-gavhane
%V 2
%X Contemporary ?eld-programmable gate array (FPGA) design requires a spectrum of available physical resources. As FPGA logic capacity has grown, locally accessed FPGA embedded memory blocks have increased in importance. When targeting FPGAs, application designers often specify high-level memory functions, which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this paper, a set of power efficient logical-to-physical RAM mapping algorithms is described, which converts user de?ned memory speci?cations to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-ef?cient choice. Our automated approach has been validated with both simulation of power dissipation and measurements of power dissipation on FPGA hardware. A comparison of measured power reductions to values determined via simulation con?rms the accuracy of our simulation approach. Our power-aware RAM mapping algorithms have been integrated into a commercial FPGA compiler and tested with 34 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 26% and overall core dynamic power can be reduced by 6% with a minimal loss (1%) in design performance. In addition, it is shown that the availability of multiple embedded memory block sizes in an FPGA reduces embedded memory dynamic power by an additional 9.6% by giving more choices to the computer-aided design algorithms. Bhagyashree Ashok Gavhane | Prashant Vitthalrao KatholeÄlternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3 , April 2018, URL: http://www.ijtsrd.com/papers/ijtsrd7172.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/7172/alternative-ram-mapping-algorithm-for-embedded-memory-blocks-in-fpga/bhagyashree-ashok-gavhane
@article{noauthororeditor,
abstract = {Contemporary ?eld-programmable gate array (FPGA) design requires a spectrum of available physical resources. As FPGA logic capacity has grown, locally accessed FPGA embedded memory blocks have increased in importance. When targeting FPGAs, application designers often specify high-level memory functions, which exhibit a range of sizes and control structures. These logical memories must be mapped to FPGA embedded memory resources such that physical design objectives are met. In this paper, a set of power efficient logical-to-physical RAM mapping algorithms is described, which converts user de?ned memory speci?cations to on-chip FPGA memory block resources. These algorithms minimize RAM dynamic power by evaluating a range of possible embedded memory block mappings and selecting the most power-ef?cient choice. Our automated approach has been validated with both simulation of power dissipation and measurements of power dissipation on FPGA hardware. A comparison of measured power reductions to values determined via simulation con?rms the accuracy of our simulation approach. Our power-aware RAM mapping algorithms have been integrated into a commercial FPGA compiler and tested with 34 large FPGA benchmarks. Through experimentation, we show that, on average, embedded memory dynamic power can be reduced by 26% and overall core dynamic power can be reduced by 6% with a minimal loss (1%) in design performance. In addition, it is shown that the availability of multiple embedded memory block sizes in an FPGA reduces embedded memory dynamic power by an additional 9.6% by giving more choices to the computer-aided design algorithms. Bhagyashree Ashok Gavhane | Prashant Vitthalrao Kathole"Alternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3 , April 2018, URL: http://www.ijtsrd.com/papers/ijtsrd7172.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/7172/alternative-ram-mapping-algorithm-for-embedded-memory-blocks-in-fpga/bhagyashree-ashok-gavhane
},
added-at = {2018-09-10T07:47:21.000+0200},
author = {Kathole, Bhagyashree Ashok Gavhane Prashant Vitthalrao},
biburl = {https://www.bibsonomy.org/bibtex/2cde2e43725ac239be0634f49437e8053/ijtsrd},
interhash = {ee6b457ea65fd46449bf546fc538b52f},
intrahash = {cde2e43725ac239be0634f49437e8053},
issn = {2456-6470},
journal = {International Journal of Trend in Scientific Research and Development},
keywords = {& (FPGAs) ?eld-programmable Communication Electronics Engineering architecture arrays automation demand designing gate memory power},
language = {English},
month = {April},
number = 3,
pages = {2542-2549},
timestamp = {2018-10-02T11:01:27.000+0200},
title = {Alternative RAM Mapping Algorithm for Embedded Memory Blocks in FPGA
},
url = {http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/7172/alternative-ram-mapping-algorithm-for-embedded-memory-blocks-in-fpga/bhagyashree-ashok-gavhane},
volume = 2,
year = 2018
}