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FPGA IMPLEMENTATION OF HIGH SPEED BAUGH-WOOLEY MULTIPLIER USING DECOMPOSITION LOGIC

. Emerging Trends in Electrical, Electronics & Instrumentation Engineering: An international Journal, 2 (3): 1-7 (August 2015)
DOI: 10.5121/eeiej.2015.2301

Abstract

In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared with booth multiplier. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device.

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