%0 Conference Paper %1 conf/eusipco/KimijimaNK98 %A Kimijima, Tadaaki %A Nishikawa, Kiyoshi %A Kiya, Hitoshi %B EUSIPCO %D 1998 %I IEEE %K dblp %P 1-4 %T A pipelined architecture for DLMS algorithm considering both hardware complexity and output latency. %U http://dblp.uni-trier.de/db/conf/eusipco/eusipco1998.html#KimijimaNK98 %@ 978-960-7620-06-4

@inproceedings{conf/eusipco/KimijimaNK98, added-at = {2021-08-09T00:00:00.000+0200}, author = {Kimijima, Tadaaki and Nishikawa, Kiyoshi and Kiya, Hitoshi}, biburl = {https://www.bibsonomy.org/bibtex/2d450650038b86c73c4bd40874f4d2d60/dblp}, booktitle = {EUSIPCO}, crossref = {conf/eusipco/1998}, ee = {https://ieeexplore.ieee.org/document/7089687/}, interhash = {76d71671e44d9537c67f449f44acc650}, intrahash = {d450650038b86c73c4bd40874f4d2d60}, isbn = {978-960-7620-06-4}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2024-04-10T21:36:39.000+0200}, title = {A pipelined architecture for DLMS algorithm considering both hardware complexity and output latency.}, url = {http://dblp.uni-trier.de/db/conf/eusipco/eusipco1998.html#KimijimaNK98}, year = 1998 }