%0 Conference Paper %1 onouchi2006systemlevel %A Onouchi, M. %A Yamada, T. %A Morikawa, K. %A Mochizuki, I. %A Sekine, H. %B ASP-DAC '06: Proceedings of the 2006 Conference on Asia South Pacific Design Automation %C New York, NY, USA %D 2006 %I ACM Press %K DAC Methodology Modelling Power estimation %P 547--550 %T A System-Level Power-Estimation Methodology Based on IP-Level Modeling, Power-Level Adjustment, and Power Accumulation %U http://doi.acm.org/10.1145/1118299.1118430 %X We have developed a specialized rapid power-estimation methodology for multimedia applications. This methodology has adequate accuracy for the first design of a complicated SoC. For a multimedia application, we developed three new methodologies: an IP-level modeling, a power-level adjustment methodology, and a power accumulation methodology. With these methodologies, the system-level power estimation on a SoC executing a practical application becomes so precise and easy that we can revise the SoC design to reduce its power. According to a comparison of the system-level power estimated with these methodologies to board-measured power, the error between the two powers is less than 5.6%. %@ 0-7803-9451-8

@inproceedings{onouchi2006systemlevel, abstract = {We have developed a specialized rapid power-estimation methodology for multimedia applications. This methodology has adequate accuracy for the first design of a complicated SoC. For a multimedia application, we developed three new methodologies: an IP-level modeling, a power-level adjustment methodology, and a power accumulation methodology. With these methodologies, the system-level power estimation on a SoC executing a practical application becomes so precise and easy that we can revise the SoC design to reduce its power. According to a comparison of the system-level power estimated with these methodologies to board-measured power, the error between the two powers is less than 5.6%.}, added-at = {2007-04-12T13:24:02.000+0200}, address = {New York, NY, USA}, author = {Onouchi, M. and Yamada, T. and Morikawa, K. and Mochizuki, I. and Sekine, H.}, biburl = {https://www.bibsonomy.org/bibtex/2d49e3b390875bfc5dbc43f2bd06f30cf/derkling}, booktitle = {ASP-DAC '06: Proceedings of the 2006 Conference on Asia South Pacific Design Automation}, hardcopy = {Yes}, interhash = {2c56bc3df3a16dcc2f56802d5b41e55d}, intrahash = {d49e3b390875bfc5dbc43f2bd06f30cf}, isbn = {0-7803-9451-8}, keywords = {DAC Methodology Modelling Power estimation}, local = {./AllPapers/2006_DAC_onouchi2006systemlevel.pdf}, pages = {547--550}, publisher = {ACM Press}, timestamp = {2007-04-12T13:24:02.000+0200}, title = {A System-Level Power-Estimation Methodology Based on IP-Level Modeling, Power-Level Adjustment, and Power Accumulation}, url = {http://doi.acm.org/10.1145/1118299.1118430}, year = 2006 }