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A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor

, , , , and . International Conference on Parallel and Distributed Systems, 14, page 689-696. Los Alamitos, CA, USA, IEEE Computer Society, (2008)
DOI: http://doi.ieeecomputersociety.org/10.1109/ICPADS.2008.18

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