%0 Journal Article %1 journals/jssc/SakashitaNSOSYT96 %A Sakashita, Narumi %A Nitta, Yasuhiko %A Shimomura, Ken'ichi %A Okuda, Fumihiro %A Shimano, Hiroki %A Yamakawa, Satoshi %A Tsukude, Masaki %A Arimoto, Kazutami %A Baba, Shinji %A Komori, Shinji %A Kyuma, Kazuo %A Yasuoka, Akihiko %A Abe, Haruhiko %D 1996 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1645-1655 %T A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. %U http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#SakashitaNSOSYT96 %V 31

@article{journals/jssc/SakashitaNSOSYT96, added-at = {2022-07-18T00:00:00.000+0200}, author = {Sakashita, Narumi and Nitta, Yasuhiko and Shimomura, Ken'ichi and Okuda, Fumihiro and Shimano, Hiroki and Yamakawa, Satoshi and Tsukude, Masaki and Arimoto, Kazutami and Baba, Shinji and Komori, Shinji and Kyuma, Kazuo and Yasuoka, Akihiko and Abe, Haruhiko}, biburl = {https://www.bibsonomy.org/bibtex/2e94fe31044b1586c36a244490f88c966/dblp}, ee = {https://doi.org/10.1109/JSSC.1996.542309}, interhash = {2deb6a2c2f933d60b202c726338bc497}, intrahash = {e94fe31044b1586c36a244490f88c966}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1645-1655}, timestamp = {2024-04-08T10:42:11.000+0200}, title = {A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#SakashitaNSOSYT96}, volume = 31, year = 1996 }