%0 Journal Article %1 journals/ieicet/IizukaIA05 %A Iizuka, Tetsuya %A Ikeda, Makoto %A Asada, Kunihiro %D 2005 %J IEICE Trans. Fundam. Electron. Commun. Comput. Sci. %K dblp %N 7 %P 1957-1963 %T Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet88a.html#IizukaIA05 %V 88-A

@article{journals/ieicet/IizukaIA05, added-at = {2020-04-11T00:00:00.000+0200}, author = {Iizuka, Tetsuya and Ikeda, Makoto and Asada, Kunihiro}, biburl = {https://www.bibsonomy.org/bibtex/2e9d991b6f609a90ec007680b6467ec3a/dblp}, ee = {https://doi.org/10.1093/ietfec/e88-a.7.1957}, interhash = {3907608869802930957bedd32ece0985}, intrahash = {e9d991b6f609a90ec007680b6467ec3a}, journal = {IEICE Trans. Fundam. Electron. Commun. Comput. Sci.}, keywords = {dblp}, number = 7, pages = {1957-1963}, timestamp = {2020-04-14T11:43:27.000+0200}, title = {Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet88a.html#IizukaIA05}, volume = {88-A}, year = 2005 }