%0 Generic %1 tang02powera %A Petrov, P. %A Orailoglu, A. %D 2002 %K Cache DATE Hardware Management %T Power Efficient Embedded Processor IP's Through Application-Specific Tag Compression in Data Caches %U http://portal.acm.org/citation.cfm?id=874360 %X In this paper, we present a methodology for power minimizationby data cache tag compression. The set of tags being accessed bythe major application loops is analyzed statically during compiletime and an efficient and optimal compression scheme is proposed.Only a very limited number of tag bits are stored in the tag array forcache conflict identification, thus achieving a significant reductionin the number of active bitlines, sense amps, and comparator cells.The underlying hardware support for dynamically compressing thetags consists of a highly cost and power efficient programmableencoder, which lies outside the cache access path, thus not affectingthe processor cycle time. A detailed VLSI implementation hasbeen performed and a number of experimental results on a set ofembedded applications and numerical kernels is reported. Energydissipation decreases of up to 95% can be observed for the tag arrays,while significant energy reductions in the range of 10%-50%are observed when amortized across the overall cache subsystem.

@misc{tang02powera, abstract = {In this paper, we present a methodology for power minimizationby data cache tag compression. The set of tags being accessed bythe major application loops is analyzed statically during compiletime and an efficient and optimal compression scheme is proposed.Only a very limited number of tag bits are stored in the tag array forcache conflict identification, thus achieving a significant reductionin the number of active bitlines, sense amps, and comparator cells.The underlying hardware support for dynamically compressing thetags consists of a highly cost and power efficient programmableencoder, which lies outside the cache access path, thus not affectingthe processor cycle time. A detailed VLSI implementation hasbeen performed and a number of experimental results on a set ofembedded applications and numerical kernels is reported. Energydissipation decreases of up to 95% can be observed for the tag arrays,while significant energy reductions in the range of 10%-50%are observed when amortized across the overall cache subsystem.}, added-at = {2007-04-12T12:30:34.000+0200}, author = {Petrov, P. and Orailoglu, A.}, biburl = {https://www.bibsonomy.org/bibtex/2f6554352f12607147663ea36f37c06d4/derkling}, interhash = {fdb28de0481cb630c972a33b22a335a5}, intrahash = {f6554352f12607147663ea36f37c06d4}, keywords = {Cache DATE Hardware Management}, text = {P. Petrov, A. Orailoglu, `Power Efficient Embedded Processor IP's through Application-Specific Tag Compression in Data Caches', in Design Automation and Test in Europe Conference (DATE), pp. 1065 -- 1071, 2002}, timestamp = {2007-04-12T12:30:34.000+0200}, title = {Power Efficient Embedded Processor IP's Through Application-Specific Tag Compression in Data Caches}, url = {http://portal.acm.org/citation.cfm?id=874360}, year = 2002 }