%0 Conference Paper %1 conf/asicon/DouPSZ17 %A Dou, Xiaoxin %A Pan, Weiwei %A Shi, Zheng %A Zheng, Yongjun %B ASICON %D 2017 %E Qin, Yajie %E Hong, Zhiliang %E Tang, Ting-Ao %I IEEE %K dblp %P 492-495 %T Design and automatic generation of area-efficient ring oscillator based addressable test chips. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2017.html#DouPSZ17 %@ 978-1-5090-6625-4

@inproceedings{conf/asicon/DouPSZ17, added-at = {2023-07-28T00:00:00.000+0200}, author = {Dou, Xiaoxin and Pan, Weiwei and Shi, Zheng and Zheng, Yongjun}, biburl = {https://www.bibsonomy.org/bibtex/245ee357fbfb33bae625300a2327d3e68/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2017}, editor = {Qin, Yajie and Hong, Zhiliang and Tang, Ting-Ao}, ee = {https://doi.org/10.1109/ASICON.2017.8252521}, interhash = {3316de27b23cfed41adb14500edac527}, intrahash = {45ee357fbfb33bae625300a2327d3e68}, isbn = {978-1-5090-6625-4}, keywords = {dblp}, pages = {492-495}, publisher = {IEEE}, timestamp = {2024-04-10T12:15:48.000+0200}, title = {Design and automatic generation of area-efficient ring oscillator based addressable test chips.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2017.html#DouPSZ17}, year = 2017 }