%0 Journal Article %1 journals/todaes/KimLV15 %A Kim, Lok-Won %A Lee, Dong-U %A Villasenor, John D. %D 2015 %J ACM Trans. Design Autom. Electr. Syst. %K dblp %N 2 %P 28:1-28:24 %T Automated Iterative Pipelining for ASIC Design. %U http://dblp.uni-trier.de/db/journals/todaes/todaes20.html#KimLV15 %V 20

@article{journals/todaes/KimLV15, added-at = {2018-11-06T00:00:00.000+0100}, author = {Kim, Lok-Won and Lee, Dong-U and Villasenor, John D.}, biburl = {https://www.bibsonomy.org/bibtex/2287af9d09984beb8ca467b9a3c162ef0/dblp}, ee = {https://doi.org/10.1145/2660768}, interhash = {3ddd629b2dca0f8abc74d071d9ed73e9}, intrahash = {287af9d09984beb8ca467b9a3c162ef0}, journal = {ACM Trans. Design Autom. Electr. Syst.}, keywords = {dblp}, number = 2, pages = {28:1-28:24}, timestamp = {2018-11-07T12:24:13.000+0100}, title = {Automated Iterative Pipelining for ASIC Design.}, url = {http://dblp.uni-trier.de/db/journals/todaes/todaes20.html#KimLV15}, volume = 20, year = 2015 }