Article,
Trade-off between pure software based and FPGA based base band processing for a real time kinematics GNSS receiver
Proc. of the 18th ION GNSS Conf., (2005)
Abstract
On the background of the upcoming European global navigation system
GALILEO and the modernization of GPS many new applications in the
'high-end' of satellite based positioning and navigation are feasible.
Especially the availability of a second and/or third frequency for
the general-purpose user allows for higher precision and faster acquisition
for kinematics applications. In the effort of implementing new algorithms
for real time kinematics, two different approaches for the base band
processing unit have been developed. One approach implements a totally
PC based software receiver, which processes the digitized intermediate
frequency within the CPU of the personal computer. The correlators
and the loop discriminators use the microcontroller of the computer,
for which a high performance computer is required. However using
a software solution has the advantage of maintaining the full control
over the base band process and the opportunity of testing different
algorithms side by side. In another approach, the whole base band
processing is performed within a field programmable gate array (FPGA)
thus reducing the load of the microprocessor considerably. In addition,
using a FPGA has the advantage of processing the digitized IF samples
in real time whereas retaining full flexibility and control over
the correlation and loop closure process. Implementing different
algorithms or channel configurations often requires a time consuming
compilation process of the FPGA configuration file. However, charging
with different configuration, total reconfiguration of the FPGA takes
only a few seconds. Both methods open the flexibility to implement
new technologies with respect to the GPS modernization and the upcoming
GALILEO by software updates and easily scales in terms of number
of correlators and channels, as the limiting factor is either CPU
performance or the number of available gates within the FPGA. For
instance the position of any correlator with respect to prompt is
adjustable during runtime and is configurable even within the FPGA
based receiver with microchip resolution or even better. While the
PC based software receiver uses a standard COTS digitizer to sample
the IF signal the FPGA based receiver processes digital samples with
six bit resolution at 40 MHz sample rate. However, both units use
the same analogue IF signal from a L1/L2 high bandwidth front-end.
The receiver front-end has a low-IF architecture with a single mixer
stage in the analog domain. An active L1 or a combined L1/L2-band
antenna is connected at the input. The two bands are separated and
are processed simultaneously in different receiver chains. At one
output it provides an IF output for the PC based software receiver
and at the other output the same signal is digitized and transferred
to the FPGA-board. Thus, it is possible to process the received signal
with both methods at the same time. The front-end consists of discrete,
high performance components and is specifically designed to provide
a highly flexible adaptation and (re-) configuration of filter structures
in the RF- and IF-section concerning bandwidth and cutoff frequency.
By using almost standard components within the same PC, both approaches
can be used simultaneously, which allows direct comparison of either
method. This paper introduces the different methods of base band
processing - PC based and FPGA based - and compares the performance
of both. Using different test environments, the precise code and
phase measurements, which are essential for real time kinematics,
is proven for both approaches.
