%0 Thesis %1 1467875 %A Marty, Michael R. %C Madison, WI, USA %D 2008 %I University of Wisconsin at Madison %K Architecture Bus Cache Hardware ManyCore MultiCore Processor Ring coherence %T Cache Coherence Techniques for Multicore Processors %U http://portal.acm.org/citation.cfm?id=1467875 %X First, we recognize that rings are emerging as a preferred on-chip interconnect. Unfortunately a ring does not preserve the total order provided by a bus. We contribute a new cache coherence protocol that exploits a ring's natural round-robin order. In doing so, we show how our new protocol achieves both fast performance and performance stability—a combination not found in prior designs. %@ 978-0-549-63405-8

@phdthesis{1467875, abstract = {First, we recognize that rings are emerging as a preferred on-chip interconnect. Unfortunately a ring does not preserve the total order provided by a bus. We contribute a new cache coherence protocol that exploits a ring's natural round-robin order. In doing so, we show how our new protocol achieves both fast performance and performance stability—a combination not found in prior designs.}, added-at = {2009-11-08T22:23:10.000+0100}, address = {Madison, WI, USA}, author = {Marty, Michael R.}, biburl = {https://www.bibsonomy.org/bibtex/26961c11c6b6a5f825848fc1e763f666a/gron}, description = {Cache coherence techniques for multicore processors}, interhash = {501b1dfcd7e57001f4fbbc0b106bb5e1}, intrahash = {6961c11c6b6a5f825848fc1e763f666a}, isbn = {978-0-549-63405-8}, keywords = {Architecture Bus Cache Hardware ManyCore MultiCore Processor Ring coherence}, note = {Adviser-Hill, Mark D.}, order_no = {AAI3314233}, publisher = {University of Wisconsin at Madison}, timestamp = {2009-11-08T22:23:10.000+0100}, title = {Cache Coherence Techniques for Multicore Processors}, url = {http://portal.acm.org/citation.cfm?id=1467875}, year = 2008 }