%0 Journal Article %1 journals/ieicet/KosakaNMI07a %A Kosaka, Daisuke %A Nagata, Makoto %A Murasaka, Yoshitaka %A Iwata, Atsushi %D 2007 %J IEICE Trans. Fundam. Electron. Commun. Comput. Sci. %K dblp %N 12 %P 2651-2660 %T Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet90a.html#KosakaNMI07a %V 90-A

@article{journals/ieicet/KosakaNMI07a, added-at = {2020-04-11T00:00:00.000+0200}, author = {Kosaka, Daisuke and Nagata, Makoto and Murasaka, Yoshitaka and Iwata, Atsushi}, biburl = {https://www.bibsonomy.org/bibtex/2fd14e9e72dbb1f88589a1a727ffc96cc/dblp}, ee = {https://doi.org/10.1093/ietfec/e90-a.12.2651}, interhash = {53cfb9c1fc90a86822ccee07d559da35}, intrahash = {fd14e9e72dbb1f88589a1a727ffc96cc}, journal = {IEICE Trans. Fundam. Electron. Commun. Comput. Sci.}, keywords = {dblp}, number = 12, pages = {2651-2660}, timestamp = {2020-04-14T11:47:46.000+0200}, title = {Chip-Level Substrate Coupling Analysis with Reference Structures for Verification.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet90a.html#KosakaNMI07a}, volume = {90-A}, year = 2007 }