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%0 Journal Article
%1 noauthororeditor
%A Denguir, Mohamed
%A Sattler, Sebastian M.
%D 2018
%J International Journal of Electronic Design and Test (JEDT)
%K Formal Verification hardware of
%N 1
%P 25-44
%T STRUCTURE-PRESERVING MODELLING OF REAL CIRCUITS BASED ON SIGNAL FLOW GRAPH
%V 1
@article{noauthororeditor,
added-at = {2018-05-05T07:12:46.000+0200},
author = {Denguir, Mohamed and Sattler, Sebastian M.},
biburl = {https://www.bibsonomy.org/bibtex/2a70269cd92df1cab905cf170e80e0404/jedtjournal},
interhash = {58a0ca20e40e6ef928fcb18a3fc313ee},
intrahash = {a70269cd92df1cab905cf170e80e0404},
journal = {International Journal of Electronic Design and Test (JEDT) },
keywords = {Formal Verification hardware of},
month = {February},
number = 1,
pages = {25-44},
timestamp = {2018-05-05T07:13:00.000+0200},
title = {STRUCTURE-PRESERVING MODELLING OF REAL CIRCUITS BASED ON SIGNAL FLOW GRAPH},
volume = 1,
year = 2018
}