%0 Conference Paper %1 9919884 %A Pozzobon, Enrico %A Renner, Sebastian %A Mottok, Jürgen %A Matoušek, Václav %B 2022 International Conference on Applied Electronics (AE) %D 2022 %K srenn %P 1-4 %R 10.1109/AE54730.2022.9919884 %T An optimized Bitsliced Masked Adder for ARM Thumb-2 Controllers %U https://ieeexplore.ieee.org/document/9919884/ %X The modular addition is used as a non-linear operation in ARX ciphers because it achieves the requirement of introducing non-linearity in a cryptographic primitive while only taking one clock cycle to execute on most modern architectures. This makes ARX ciphers especially fast in software implementations, but comes at the cost of making it harder to protect against side-channel information leakages using Boolean masking: the best known 2-shares masked adder for ARM Thumb micro-controllers takes 83 instructions to add two 32-bit numbers together. Our approach is to operate in bitsliced mode, performing 32 additions in parallel on a 32-bit microcontroller. We show that, even after taking into account the cost of bitslicing before and after the encryption, it is possible to achieve a higher throughput on the tested ciphers (CRAX and ChaCha20) when operating in bitsliced mode. Furthermore, we prove that no first-order information leakage is happening in either simulated power traces and power traces acquired from real hardware, after sufficient countermeasures are put into place to guard against pipeline leakages.

@inproceedings{9919884, abstract = {The modular addition is used as a non-linear operation in ARX ciphers because it achieves the requirement of introducing non-linearity in a cryptographic primitive while only taking one clock cycle to execute on most modern architectures. This makes ARX ciphers especially fast in software implementations, but comes at the cost of making it harder to protect against side-channel information leakages using Boolean masking: the best known 2-shares masked adder for ARM Thumb micro-controllers takes 83 instructions to add two 32-bit numbers together. Our approach is to operate in bitsliced mode, performing 32 additions in parallel on a 32-bit microcontroller. We show that, even after taking into account the cost of bitslicing before and after the encryption, it is possible to achieve a higher throughput on the tested ciphers (CRAX and ChaCha20) when operating in bitsliced mode. Furthermore, we prove that no first-order information leakage is happening in either simulated power traces and power traces acquired from real hardware, after sufficient countermeasures are put into place to guard against pipeline leakages.}, added-at = {2022-11-09T11:33:54.000+0100}, author = {Pozzobon, Enrico and Renner, Sebastian and Mottok, Jürgen and Matoušek, Václav}, biburl = {https://www.bibsonomy.org/bibtex/26575af8eba7919b2d4568208b66b111e/baywiss1}, booktitle = {2022 International Conference on Applied Electronics (AE)}, doi = {10.1109/AE54730.2022.9919884}, interhash = {5a5c36b05da05f73122177578a0c7233}, intrahash = {6575af8eba7919b2d4568208b66b111e}, issn = {1805-9597}, keywords = {srenn}, month = {Sep.}, pages = {1-4}, timestamp = {2022-11-09T11:33:54.000+0100}, title = {An optimized Bitsliced Masked Adder for ARM Thumb-2 Controllers}, url = {https://ieeexplore.ieee.org/document/9919884/}, year = 2022 }