%0 Journal Article %1 noauthororeditor %A Raghuwanshi, Vidhyasagar Chaudhary | Dr. Neetesh %D 2021 %J International Journal of Trend in Scientific Research and Development %K VLSI consumption power %N 4 %P 1358-1361 %T A Survey Paper on Leakage Power and Delay in CMOS Circuits %U https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary %V 5 %X Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi Ä Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary

@article{noauthororeditor, abstract = {Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi "A Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary }, added-at = {2021-07-15T12:26:12.000+0200}, author = {Raghuwanshi, Vidhyasagar Chaudhary | Dr. Neetesh}, biburl = {https://www.bibsonomy.org/bibtex/256dbfe12602112de3841e086bec4deb4/ijtsrd}, interhash = {5c3e9c9322a2b28641f322104eab0814}, intrahash = {56dbfe12602112de3841e086bec4deb4}, issn = {2456-6470}, journal = {International Journal of Trend in Scientific Research and Development}, keywords = {VLSI consumption power}, language = {english}, month = jun, number = 4, pages = {1358-1361}, timestamp = {2021-07-15T12:26:12.000+0200}, title = {A Survey Paper on Leakage Power and Delay in CMOS Circuits }, url = {https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary}, volume = 5, year = 2021 }