%0 Generic %1 hajare2014design %A Hajare, Shweta %A P.K.Dakhole, %A and Manisha Khorgade, %D 2014 %I ACEEE (A Computer division of IDES) %K MVL(Multiple Quaternary etc latch logic) mux quaternary valued %T Design of Gates in Multiple Valued Logic %U http://searchdl.org/public/conference/2014/ITC/94.pdf %X Multiple-valued logic (MVL) application in the design of digital devices opens additional opportunities. In this paper we have designed Quaternary latch & quaternary multiplexer. Multiplexer is designed with different threshold voltages. All the circuits were simulated with the Spice tool using TSMC 250 nm technology and have shown improvements in performance and power consumption and propagation delay than their equivalent binary circuits.

@conference{hajare2014design, abstract = {Multiple-valued logic (MVL) application in the design of digital devices opens additional opportunities. In this paper we have designed Quaternary latch & quaternary multiplexer. Multiplexer is designed with different threshold voltages. All the circuits were simulated with the Spice tool using TSMC 250 nm technology and have shown improvements in performance and power consumption and propagation delay than their equivalent binary circuits.}, added-at = {2014-03-24T05:56:18.000+0100}, author = {Hajare, Shweta and P.K.Dakhole and and Manisha Khorgade}, biburl = {https://www.bibsonomy.org/bibtex/2cf7bfb3d1383bfdb1e99a5a81978c5ab/idescitation}, interhash = {66ebdbac8c0d7865ce0593053140c8d6}, intrahash = {cf7bfb3d1383bfdb1e99a5a81978c5ab}, keywords = {MVL(Multiple Quaternary etc latch logic) mux quaternary valued}, organization = {Institute of Doctors Engineers and Scientists}, publisher = {ACEEE (A Computer division of IDES)}, timestamp = {2014-03-24T05:56:18.000+0100}, title = {Design of Gates in Multiple Valued Logic}, url = {http://searchdl.org/public/conference/2014/ITC/94.pdf}, year = 2014 }