%0 Conference Paper %1 conf/vlsic/XuOI21 %A Xu, Zule %A Osada, Masaru %A Iizuka, Tetsuya %B VLSI Circuits %D 2021 %I IEEE %K dblp %P 1-2 %T A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#XuOI21 %@ 978-4-86348-780-2

@inproceedings{conf/vlsic/XuOI21, added-at = {2021-08-02T00:00:00.000+0200}, author = {Xu, Zule and Osada, Masaru and Iizuka, Tetsuya}, biburl = {https://www.bibsonomy.org/bibtex/2861f266974ec2d8a049bd99ea7a74bf8/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2021}, ee = {https://doi.org/10.23919/VLSICircuits52068.2021.9492381}, interhash = {74a949ef726fad82f41de00db754cc85}, intrahash = {861f266974ec2d8a049bd99ea7a74bf8}, isbn = {978-4-86348-780-2}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T21:13:43.000+0200}, title = {A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#XuOI21}, year = 2021 }