Please log in to take part in the discussion (add own reviews or comments).
Cite this publication
More citation styles
- please select -
%0 Conference Paper
%1 conf/iscas/MullerWSKS04
%A Müller, Matthias
%A Wortmann, Andreas
%A Simon, Sven
%A Kugel, Michael
%A Schoenauer, Tim
%B ISCAS (2)
%D 2004
%I IEEE
%K
%P 609-612
%T The impact of clock gating schemes on the power dissipation of synthesizable register files.
%U http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#MullerWSKS04
%@ 0-7803-8251-X
@inproceedings{conf/iscas/MullerWSKS04,
added-at = {2023-12-13T03:07:09.000+0100},
author = {Müller, Matthias and Wortmann, Andreas and Simon, Sven and Kugel, Michael and Schoenauer, Tim},
biburl = {https://www.bibsonomy.org/bibtex/2a319b20875d2c9b8ff9c9e19abdbb779/admin},
booktitle = {ISCAS (2)},
crossref = {conf/iscas/2004},
ee = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255},
interhash = {87b60cb07894803e8ffea512012d6d4b},
intrahash = {a319b20875d2c9b8ff9c9e19abdbb779},
isbn = {0-7803-8251-X},
keywords = {},
pages = {609-612},
publisher = {IEEE},
timestamp = {2023-12-13T03:07:09.000+0100},
title = {The impact of clock gating schemes on the power dissipation of synthesizable register files.},
url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#MullerWSKS04},
year = 2004
}