Article,

ON VERTICAL INTEGRATION FRAMEWORK ELEMENT OF TRANSISTOR-TRANSISTOR LOGIC

, and .
International Journal of Applied Control, Electrical and Electronics Engineering, 3 (3): 1-23 (August 2015)
DOI: 10.5121

Abstract

In this paper we introduce an approach to increase vertical integration of elements of transistor-transistor logic with function AND-NOT. Framework the approach we consider a heterostructure with special configuration.Several specific areas of the heterostructure should be doped by diffusion or ion implantation.Annealing of dopant and/or radiation defects should be optimized.

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