%0 Journal Article %1 journals/jssc/MizunoMOSOIIK96 %A Mizuno, Hiroyuki %A Matsuzaki, Nozomu %A Osada, Kenichi %A Shinbo, Toshinobu %A Ohki, Nagatoshi %A Ishida, Hiroshi %A Ishibashi, Koichiro %A Kure, Tokuo %D 1996 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1618-1624 %T A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. %U http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#MizunoMOSOIIK96 %V 31

@article{journals/jssc/MizunoMOSOIIK96, added-at = {2022-10-02T00:00:00.000+0200}, author = {Mizuno, Hiroyuki and Matsuzaki, Nozomu and Osada, Kenichi and Shinbo, Toshinobu and Ohki, Nagatoshi and Ishida, Hiroshi and Ishibashi, Koichiro and Kure, Tokuo}, biburl = {https://www.bibsonomy.org/bibtex/22f00d0d26152efab22b7e085c4da4adc/dblp}, ee = {https://doi.org/10.1109/JSSC.1996.542306}, interhash = {9e10ecd43370e522c69c37fa25703e2c}, intrahash = {2f00d0d26152efab22b7e085c4da4adc}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1618-1624}, timestamp = {2024-04-08T10:43:09.000+0200}, title = {A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#MizunoMOSOIIK96}, volume = 31, year = 1996 }