%0 Generic %1 shankaranarayanan2013simulation %B 2013 Mobile Communication - II %D 2013 %E Shankaranarayanan, Dr. %I ACEEE (A Computer division of IDES) %K CMOS Cadence- Low Virtuoso circuits dynamic power %T A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverter %U http://searchdl.org/public/book_series/LSCS/3/526.pdf %X With the increase in demand of high fidelity portable devices, there is more and more emphasis laying down on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as adder. CMOS circuit design plays a crucial role in designing of these computation units (like adder and multiplier) so if there is any optimal way to reduce the power dissipation in CMOS circuits then it will directly lower down the power dissipation of other circuits and logic gates as well. In this paper we have studied and analyzed different techniques to reduce the dynamic power of CMOS circuit with the help of performing simulation on some significant factors (i.e device characteristics) of respective circuitry designs by using Cadence-Virtuoso tool.

@conference{shankaranarayanan2013simulation, abstract = {With the increase in demand of high fidelity portable devices, there is more and more emphasis laying down on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as adder. CMOS circuit design plays a crucial role in designing of these computation units (like adder and multiplier) so if there is any optimal way to reduce the power dissipation in CMOS circuits then it will directly lower down the power dissipation of other circuits and logic gates as well. In this paper we have studied and analyzed different techniques to reduce the dynamic power of CMOS circuit with the help of performing simulation on some significant factors (i.e device characteristics) of respective circuitry designs by using Cadence-Virtuoso tool.}, added-at = {2014-02-05T06:38:11.000+0100}, biburl = {https://www.bibsonomy.org/bibtex/28e877ea05b078724e93a084fcb01a802/idescitation}, booktitle = {2013 Mobile Communication - II}, editor = {Shankaranarayanan, Dr.}, interhash = {a4342be415d6da1a59e3e5495aecab7a}, intrahash = {8e877ea05b078724e93a084fcb01a802}, keywords = {CMOS Cadence- Low Virtuoso circuits dynamic power}, organization = {Institute of Doctors Engineers and Scientists}, publisher = {ACEEE (A Computer division of IDES)}, timestamp = {2014-02-05T06:38:11.000+0100}, title = {A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverter}, url = {http://searchdl.org/public/book_series/LSCS/3/526.pdf}, year = 2013 }