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Design D Flip-Flop for Low Power Application
International Journal of Innovative Science and Modern Engineering (IJISME), 4 (6): 11-15 (июня 2016)
Аннотация
Power consumption is a major problem of system performance and it is listed as one of the top three challenges in International Technology for Semiconductor. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flip-flops. In this thesis, various design techniques for a low power clocking system are surveyed. Among them minimizing a number of clocked transistor is an effective way to reduce capacity of the clock load. To approach this, we propose a conditional data mapping technique which reduces the number of local clocked transistors.
