%0 Journal Article %1 journals/integration/WilleSSD16 %A Wille, Robert %A Schönborn, Eleonora %A Soeken, Mathias %A Drechsler, Rolf %D 2016 %J Integr. %K %P 39-53 %T SyReC: A hardware description language for the specification and synthesis of reversible circuits. %U http://dblp.uni-trier.de/db/journals/integration/integration53.html#WilleSSD16 %V 53

@article{journals/integration/WilleSSD16, added-at = {2023-12-13T07:58:35.000+0100}, author = {Wille, Robert and Schönborn, Eleonora and Soeken, Mathias and Drechsler, Rolf}, biburl = {https://www.bibsonomy.org/bibtex/2933076f69cb01859c7a2629071fc5f2a/admin}, ee = {https://www.wikidata.org/entity/Q59242088}, interhash = {bf6ebc68a5fc0e0aa423b61e5cb38dd3}, intrahash = {933076f69cb01859c7a2629071fc5f2a}, journal = {Integr.}, keywords = {}, pages = {39-53}, timestamp = {2023-12-13T07:58:35.000+0100}, title = {SyReC: A hardware description language for the specification and synthesis of reversible circuits.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration53.html#WilleSSD16}, volume = 53, year = 2016 }