Abstract
ARM introduced the Advanced Microcontroller Bus
Architecture (AMBA) 4.0 and its specifications define five
buses/interfaces: Advanced eXtensible Interface Bus (AXI),
Advanced High-performance Bus (AHB), Advanced System Bus
(ASB), Advanced Peripheral Bus (APB) and Advanced Trace
Bus (ATB). That means more and more existing Intellectual
Property (IP) must be able to communicate with AMBA4.0
bus. This paper presents an IP core design of APB Bridge, to
provide interface between AXI-Lite bus and APB bus operating
at different frequencies. The maximum operating frequency
of the module is 168.464MHz. Test cases are run to perform
multiple read and write operations. Synthesis and Simulation
is done using Xilinx ISE and Modelsim.
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