%0 Conference Paper %1 conf/date/ShonikerCHP15 %A Shoniker, Michael %A Cockburn, Bruce F. %A Han, Jie %A Pedrycz, Witold %B DATE %D 2015 %E Nebel, Wolfgang %E Atienza, David %I ACM %K dblp %P 289-292 %T Minimizing the number of process corner simulations during design verification. %U http://dblp.uni-trier.de/db/conf/date/date2015.html#ShonikerCHP15 %@ 978-3-9815370-4-8

@inproceedings{conf/date/ShonikerCHP15, added-at = {2021-08-09T00:00:00.000+0200}, author = {Shoniker, Michael and Cockburn, Bruce F. and Han, Jie and Pedrycz, Witold}, biburl = {https://www.bibsonomy.org/bibtex/24743ea32a3503b706955bef1588fcb11/dblp}, booktitle = {DATE}, crossref = {conf/date/2015}, editor = {Nebel, Wolfgang and Atienza, David}, ee = {https://ieeexplore.ieee.org/document/7092399/}, interhash = {c8ac106e87d5d2eb28976ed5230fe600}, intrahash = {4743ea32a3503b706955bef1588fcb11}, isbn = {978-3-9815370-4-8}, keywords = {dblp}, pages = {289-292}, publisher = {ACM}, timestamp = {2024-04-10T06:47:29.000+0200}, title = {Minimizing the number of process corner simulations during design verification.}, url = {http://dblp.uni-trier.de/db/conf/date/date2015.html#ShonikerCHP15}, year = 2015 }