%0 Journal Article %1 hoskote20075 %A Hoskote, Y. %A Vangal, S. %A Singh, A. %A Borkar, N. %A Borkar, S. %D 2007 %I IEEE %J Micro, IEEE %K mesh on-chip %N 5 %P 51--61 %R 10.1109/MM.2007.4378783 %T A 5-GHz mesh interconnect for a teraflops processor %V 27 %X A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.

@article{hoskote20075, abstract = {A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.}, added-at = {2012-11-20T20:17:22.000+0100}, author = {Hoskote, Y. and Vangal, S. and Singh, A. and Borkar, N. and Borkar, S.}, biburl = {https://www.bibsonomy.org/bibtex/2a1629d3f6756469f252b5a5ae1a20bc6/ytyoun}, doi = {10.1109/MM.2007.4378783}, interhash = {d02667e6962bb8906bfaca385c3236dc}, intrahash = {a1629d3f6756469f252b5a5ae1a20bc6}, journal = {Micro, IEEE}, keywords = {mesh on-chip}, number = 5, pages = {51--61}, publisher = {IEEE}, timestamp = {2012-11-20T20:17:22.000+0100}, title = {A {5-GHz} mesh interconnect for a teraflops processor}, volume = 27, year = 2007 }