%0 Journal Article %1 journals/tcad/PaleskoA83 %A Palesko, Chet A. %A Akers, Lex A. %D 1983 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 2 %P 117-121 %T Logic Partitioning for Minimizing Gate Arrays. %U http://dblp.uni-trier.de/db/journals/tcad/tcad2.html#PaleskoA83 %V 2

@article{journals/tcad/PaleskoA83, added-at = {2020-09-24T00:00:00.000+0200}, author = {Palesko, Chet A. and Akers, Lex A.}, biburl = {https://www.bibsonomy.org/bibtex/2e67cd4d19e6aaaa2613a999a47a1a741/dblp}, ee = {https://doi.org/10.1109/TCAD.1983.1270028}, interhash = {d0ed8e5a4b0a9960ee0df3f9efe4a59d}, intrahash = {e67cd4d19e6aaaa2613a999a47a1a741}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 2, pages = {117-121}, timestamp = {2020-09-25T11:48:28.000+0200}, title = {Logic Partitioning for Minimizing Gate Arrays.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad2.html#PaleskoA83}, volume = 2, year = 1983 }