%0 Conference Paper %1 kadayif02energysaving %A Kadayif, I. %A Kandemir, M. %A Karakoy, M. %B DAC '02: Proceedings of the 39th Conference on Design Automation %C New York, NY, USA %D 2002 %I ACM Press %K Adaptive Applications DATE Loop Parallelization %P 195--200 %T An Energy Saving Strategy Based on Adaptive Loop Parallelization %U http://doi.acm.org/10.1145/513918.513968 %X In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop in a multi-processor on-a-chip (MPoC) are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67% energy savings with up to 17% performance loss in a set of array-intensive applications. We also discuss and evaluate a processor pre-activation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut-down and pre-activation can be very effective in reducing energy consumption without increasing execution time. %@ 1-58113-461-4

@inproceedings{kadayif02energysaving, abstract = {In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop in a multi-processor on-a-chip (MPoC) are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67% energy savings with up to 17% performance loss in a set of array-intensive applications. We also discuss and evaluate a processor pre-activation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut-down and pre-activation can be very effective in reducing energy consumption without increasing execution time.}, added-at = {2007-04-12T12:53:54.000+0200}, address = {New York, NY, USA}, author = {Kadayif, I. and Kandemir, M. and Karakoy, M.}, biburl = {https://www.bibsonomy.org/bibtex/2ac89fde17caa8fe438317a67f7d76ab2/derkling}, booktitle = {DAC '02: Proceedings of the 39th Conference on Design Automation}, interhash = {d61d51937f4858bbf7758c19216eaf90}, intrahash = {ac89fde17caa8fe438317a67f7d76ab2}, isbn = {1-58113-461-4}, keywords = {Adaptive Applications DATE Loop Parallelization}, location = {New Orleans, Louisiana, USA}, pages = {195--200}, publisher = {ACM Press}, text = {Kadayif, I., Kandemir, M., and Karakoy, M. 2002. An energy saving strategy based on adaptive loop parallelization. In Proceedings of the 39th Conference on Design Automation (New Orleans, Louisiana, USA, June 10 - 14, 2002). DAC '02. ACM Press, New York, NY, 195-200.}, timestamp = {2007-04-12T12:53:55.000+0200}, title = {An Energy Saving Strategy Based on Adaptive Loop Parallelization}, url = {http://doi.acm.org/10.1145/513918.513968}, year = 2002 }