%0 Journal Article %1 journals/tpds/RamosH16 %A Ramos, Sabela %A Hoefler, Torsten %D 2016 %J IEEE Trans. Parallel Distributed Syst. %K dblp %N 10 %P 2824-2837 %T Cache Line Aware Algorithm Design for Cache-Coherent Architectures. %U http://dblp.uni-trier.de/db/journals/tpds/tpds27.html#RamosH16 %V 27

@article{journals/tpds/RamosH16, added-at = {2020-10-02T00:00:00.000+0200}, author = {Ramos, Sabela and Hoefler, Torsten}, biburl = {https://www.bibsonomy.org/bibtex/252ebe78dc1eff9284fb65408a297eb47/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TPDS.2016.2516540}, interhash = {e1a4ea70f0e8981331c9ae6f2fd98eda}, intrahash = {52ebe78dc1eff9284fb65408a297eb47}, journal = {IEEE Trans. Parallel Distributed Syst.}, keywords = {dblp}, number = 10, pages = {2824-2837}, timestamp = {2020-10-03T11:38:03.000+0200}, title = {Cache Line Aware Algorithm Design for Cache-Coherent Architectures.}, url = {http://dblp.uni-trier.de/db/journals/tpds/tpds27.html#RamosH16}, volume = 27, year = 2016 }