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A Novel Implementation of RISI Controller Employing Adaptive Clock Gating Technique
International Journal of Advanced Computer Science and Applications(IJACSA), (2011)
Аннотация
With the scaling of technology and the need for higher performance and more functionality power dissipation is becoming a major issue for controller design. Interrupt based programming is widely used for interfacing a processor with peripherals. The proposed architecture implements a mechanism which combines interrupt controller and RIS (Reduced Instruction Set) CPU (Central processing unit) on a single die. RISI Controller takes only one cycle for both interrupt request generation and acknowledgement. The architecture have a dynamic control unit which consists of a program flow controller, interrupt controller and I/O controller. Adaptive clock gating technique is used to reduce power consumption in the dynamic control unit. The controller consumes a power of 174&\#181;w@1MHz and is implemented in verilog HDL using Xilinx platform
