%0 Journal Article %1 doi:10.1117/12.2035457 %A Byszuk, Adrian %A Kolasiński, Piotr %A Poźniak, Krzysztof %A Zabołotny, Wojciech M. %A Kasprowicz, Grzegorz %D 2013 %E Romaniuk, Ryszard S. %J Proc. SPIE %K myown %P 89032A-89032A-6 %R 10.1117/12.2035457 %T Implementation of PCIe-SerDes-DDR3 communication in a multi-FPGA data acquisition system %U /brokenurl# http://dx.doi.org/10.1117/12.2035457 %V 8903 %X This paper describes the embedded system used to store and transfer large amounts of data in a multichannel data acquisition system for the GEM detector. The stored data is used for diagnostics purposes. System consists of an embedded mini ITX motherboard connected through the PCI Express (PCIe) link to a backplane FPGA. The backplane FPGA is connected through the SerDes/GTP links to (up to) 4 carrier boards. Each carrier board is connected to (up to) 4 FMC modules. System allows for a high speed data transfers between the ITX motherboard and the backplane or carrier modules. Due to high performance/reliability requirements, special care is taken for a proper data error correction/packet retransmission scenarios. There is also need for a proper communications diagnostics and a system addressing abstraction. Due to a distributed nature of described data acquisition system, data stored in DDR memory has to have a specific structure. This structure allows for a proper synchronisation of data between all the carrier boards.

@article{doi:10.1117/12.2035457, abstract = {This paper describes the embedded system used to store and transfer large amounts of data in a multichannel data acquisition system for the GEM detector. The stored data is used for diagnostics purposes. System consists of an embedded mini ITX motherboard connected through the PCI Express (PCIe) link to a backplane FPGA. The backplane FPGA is connected through the SerDes/GTP links to (up to) 4 carrier boards. Each carrier board is connected to (up to) 4 FMC modules. System allows for a high speed data transfers between the ITX motherboard and the backplane or carrier modules. Due to high performance/reliability requirements, special care is taken for a proper data error correction/packet retransmission scenarios. There is also need for a proper communications diagnostics and a system addressing abstraction. Due to a distributed nature of described data acquisition system, data stored in DDR memory has to have a specific structure. This structure allows for a proper synchronisation of data between all the carrier boards. }, added-at = {2013-10-29T21:35:13.000+0100}, author = {Byszuk, Adrian and Kolasiński, Piotr and Poźniak, Krzysztof and Zabołotny, Wojciech M. and Kasprowicz, Grzegorz}, biburl = {https://www.bibsonomy.org/bibtex/209dd22fc0b6b214801d943d150f13524/wzab}, doi = {10.1117/12.2035457}, editor = {Romaniuk, Ryszard S.}, interhash = {ee747b9ae16a48caf25f2a41f33f3c61}, intrahash = {09dd22fc0b6b214801d943d150f13524}, journal = {Proc. SPIE}, keywords = {myown}, pages = {89032A-89032A-6}, timestamp = {2013-10-29T21:35:13.000+0100}, title = {Implementation of PCIe-SerDes-DDR3 communication in a multi-FPGA data acquisition system }, url = {/brokenurl# http://dx.doi.org/10.1117/12.2035457}, volume = 8903, year = 2013 }