%0 Conference Paper %1 conf/iscas/ChengHTPC05 %A Cheng, Chih-Chi %A Huang, Chao-Tsung %A Tseng, Po-Chih %A Pan, Chia-Ho %A Chen, Liang-Gee %B ISCAS (5) %D 2005 %I IEEE %K dblp %P 5190-5193 %T Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2005-5.html#ChengHTPC05 %@ 0-7803-8834-8

@inproceedings{conf/iscas/ChengHTPC05, added-at = {2007-12-03T00:00:00.000+0100}, author = {Cheng, Chih-Chi and Huang, Chao-Tsung and Tseng, Po-Chih and Pan, Chia-Ho and Chen, Liang-Gee}, biburl = {https://www.bibsonomy.org/bibtex/2cbc1b9d99bfb8a2d41d5a9e8b573d974/dblp}, booktitle = {ISCAS (5)}, crossref = {conf/iscas/2005}, ee = {http://dx.doi.org/10.1109/ISCAS.2005.1465804}, interhash = {fc92cd5b73d633d2d4bf71800c25458b}, intrahash = {cbc1b9d99bfb8a2d41d5a9e8b573d974}, isbn = {0-7803-8834-8}, keywords = {dblp}, pages = {5190-5193}, publisher = {IEEE}, timestamp = {2016-05-21T12:01:14.000+0200}, title = {Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2005-5.html#ChengHTPC05}, year = 2005 }