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Другие публикации лиц с тем же именем

An LPGA with Foldable PLA-style Logic Blocks., и . FPGA, стр. 244-252. ACM, (1998)LegUp: high-level synthesis for FPGA-based processor/accelerator systems., , , , , , , и . FPGA, стр. 33-36. ACM, (2011)Towards interconnect-adaptive packing for FPGAs., , и . FPGA, стр. 21-30. ACM, (2014)FPGA power reduction by guarded evaluation., и . FPGA, стр. 157-166. ACM, (2010)Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework., , , , , , и . ISPD, стр. 48-55. ACM, (2018)Clock gating architectures for FPGA power reduction., , и . FPL, стр. 112-118. IEEE, (2009)Design re-use for compile time reduction in FPGA high-level synthesis flows., и . FPT, стр. 4-11. IEEE, (2014)Generic Connectivity-Based CGRA Mapping via Integer Linear Programming., и . FCCM, стр. 65-73. IEEE, (2019)Optimizing FPGA Logic Block Architectures for Arithmetic., , , , , , , , , и 2 other автор(ы). IEEE Trans. Very Large Scale Integr. Syst., 28 (6): 1378-1391 (2020)Area-Driven FPGA Logic Synthesis Using Reinforcement Learning., и . ASP-DAC, стр. 159-165. ACM, (2023)