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13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.

, , , , , , , , , , , и . ISSCC, стр. 222-224. IEEE, (2020)

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Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 54 (4): 1029-1038 (2019)A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application., , , , и . A-SSCC, стр. 9-12. IEEE, (2017)A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation., , и . J. Low Power Electron., 9 (1): 9-22 (2013)A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 494-495. IEEE, (2023)Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (3): 188-192 (2014)13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 222-224. IEEE, (2020)Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time., , , , , , , , , и 2 other автор(ы). VLSI Circuits, стр. 79-80. IEEE, (2018)