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BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.

T. Gu, W. Li, A. Zhao, Z. Bi, X. Li, F. Yang, C. Yan, W. Hu, D. Zhou, T. Cui, X. Liu, Z. Zhang, и X. Zeng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 417-430 (февраля 2024)

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Hongguang Bi

Bi Wu

Bi Yu

Shasha Bi

Bi Zhao

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Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework.L. Qian, Z. Bi, D. Zhou, и X. Zeng. IEEE Trans. Very Large Scale Integr. Syst., 23 (11): 2595-2605 (2015)A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.J. Zhao, C. Yan, Z. Bi, F. Yang, X. Zeng, и D. Zhou. ASP-DAC, стр. 86-91. IEEE, (2022)Analog circuit performance bound estimation based on extreme value theory.M. Li, Z. Bi, D. Zhou, и X. Zeng. MWSCAS, стр. 1-4. IEEE, (2015)Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative.Y. Wang, Z. Bi, Y. Xie, T. Wu, X. Zeng, S. Chen, и D. Zhou. IEEE J. Biomed. Health Informatics, 26 (3): 1239-1250 (2022)Optimization and Quality Estimation of Circuit Design via Random Region Covering Method.Z. Bi, D. Zhou, S. Wang, и X. Zeng. ACM Trans. Design Autom. Electr. Syst., 23 (1): 1:1-1:25 (2017)BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.T. Gu, W. Li, A. Zhao, Z. Bi, X. Li, F. Yang, C. Yan, W. Hu, D. Zhou, T. Cui и 3 other автор(ы). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (2): 417-430 (февраля 2024)A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.B. He, S. Zhang, Y. Wang, T. Gao, F. Yang, C. Yan, D. Zhou, Z. Bi, и X. Zeng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 347-359 (февраля 2023)A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.X. Fu, C. Yan, Z. Bi, F. Yang, D. Zhou, и X. Zeng. ISCAS, стр. 2886-2890. IEEE, (2022)cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.A. Zhao, X. Wang, Z. Lin, Z. Bi, X. Li, C. Yan, F. Yang, L. Shang, D. Zhou, и X. Zeng. DAC, стр. 1-6. IEEE, (2023)Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.Y. Yang, H. Zhu, Z. Bi, C. Yan, D. Zhou, Y. Su, и X. Zeng. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (3): 531-544 (2018)

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