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Другие публикации лиц с тем же именем

VLSI architecture of dynamically reconfigurable hardware-based cipher., , , и . ISCAS (4), стр. 734-737. IEEE, (2001)Burst mode: a new acceleration mode for 128-bit block ciphers., , , и . CICC, стр. 151-154. IEEE, (2002)A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture., , , , , и . FPL, стр. 615-618. IEEE, (2012)Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis., , , , , , , , , и 2 other автор(ы). ASP-DAC, стр. 14-15. IEEE, (2015)An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability., , , , и . IEICE Trans. Electron., 92-C (2): 281-285 (2009)NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode., , , , и . PATMOS, том 6951 из Lecture Notes in Computer Science, стр. 152-161. Springer, (2011)Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution., , , и . ISQED, стр. 839-844. IEEE, (2010)Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration., , , и . ISQED, стр. 646-651. IEEE, (2010)Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits., , , и . ISLPED, стр. 51-56. ACM, (2009)A dynamically reconfigurable hardware-based cipher chip., , , и . ASP-DAC, стр. 11-12. ACM, (2001)