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An integrated approach to developing manufacturing control software.

, , и . ICRA, стр. 1979-1984. IEEE Computer Society, (1991)

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Georg Davidson

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G Davidson

 

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Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (12): 1526-1545 (1995)Author retrospective for optimum modulo schedules for minimum register requirements., , и . ICS 25th Anniversary, стр. 35-36. ACM, (2014)An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels., и . ICS, стр. 510-518. ACM, (1988)Performance of Shared Cache for Parallel-Pipelined Computer Systems, , и . ISCA, стр. 117-123. ACM, (1983)Design of Instruction Set Architectures for Support of High-Level Languages ., и . ISCA, стр. 198-206. ACM, (1984)The Cedar System and an Initial Performance Study., , , , и . 25 Years ISCA: Retrospectives and Reprints, стр. 462-472. ACM, (1998)TAXI: Trace Analysis for X86 Interpretation., и . ICCD, стр. 508-514. IEEE Computer Society, (2002)Stage scheduling: a technique to reduce the register requirements of a modulo schedule., и . MICRO, стр. 338-349. ACM / IEEE Computer Society, (1995)Probabilistic Predicate-Aware Modulo Scheduling., , и . CGO, стр. 151-162. IEEE Computer Society, (2004)Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining., , и . IEEE PACT, стр. 3-12. IEEE Computer Society, (2000)