From post

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.

, , и . IEEE Trans. Very Large Scale Integr. Syst., 20 (5): 804-817 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Parallel Decodable Two-Level Unequal Burst Error Correcting Codes., и . IEEE Trans. Computers, 64 (10): 2902-2911 (2015)Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)., и . IEEE Trans. Computers, 68 (2): 301-306 (2019)Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems., и . IEEE Trans. Computers, 65 (12): 3794-3801 (2016)Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits., и . IEEE Trans. Computers, 60 (10): 1459-1470 (2011)L band circularly polarized SAR onboard microsatellite., , , , , , , , , и 3 other автор(ы). IGARSS, стр. 5382-5385. IEEE, (2017)Extending Non-Volatile Operation to DRAM Cells., , и . IEEE Access, (2013)New 4T-based DRAM cell designs., , и . ACM Great Lakes Symposium on VLSI, стр. 199-204. ACM, (2014)Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement., , и . IEICE Trans. Inf. Syst., 97-D (3): 533-540 (2014)Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (9): 2295-2303 (2009)Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (6): 1426-1430 (2002)