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Efficient Encoding and Termination of Low-Density Parity-Check Convolutional Codes., , , и . GLOBECOM, IEEE, (2006)Design of a 3-D fully depleted SOI computational RAM., , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 13 (3): 358-369 (2005)Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders., , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (4): 836-849 (2010)Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (11): 3628-3640 (2008)Test and Characterization of a Variable-Capacity Multilevel DRAM., , , , , , , , , и . VTS, стр. 189-197. IEEE Computer Society, (2005)Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder., , , и . SiPS, стр. 294-299. IEEE, (2012)Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density., , и . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (12): 2595-2605 (2006)Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder., , , , , , и . IEEE J. Solid State Circuits, 42 (10): 2245-2256 (2007)Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders., , и . ISCAS (5), стр. 4513-4516. IEEE, (2005)Design of an Embedded Fully-Depleted SOI SRAM., , , , и . MTDT, стр. 13-. IEEE Computer Society, (2001)