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Optimizing average-case delay in technology mapping of burst-mode circuits.

, , и . ASYNC, стр. 244-260. IEEE Computer Society, (1996)

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Ihnsik Yun

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A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits., , и . EURO-DAC, стр. 284-289. IEEE Computer Society Press, (1996)Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines., и . ARVLSI, стр. 200-214. IEEE Computer Society, (1999)Optimizing average-case delay in technology mapping of burst-mode circuits., , и . ASYNC, стр. 244-260. IEEE Computer Society, (1996)A self-timed real-time sorting network., , , , и . ICCD, стр. 427-434. IEEE Computer Society, (1998)Practical Advances in Asynchronous Design., , и . ICCD, стр. 662-668. IEEE Computer Society, (1997)Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces., , и . DAC, стр. 104-109. ACM Press, (1999)Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations)., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 101-117 (1999)BDD-based synthesis of extended burst-mode controllers., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (9): 782-792 (1998)Min-max timing analysis and an application to asynchronous circuits., , и . Proc. IEEE, 87 (2): 332-346 (1999)High-performance asynchronous pipeline circuits., , и . ASYNC, стр. 17-28. IEEE Computer Society, (1996)