( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints.

, , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (3): 447-459 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

No persons found for author name Nedelchev, Ivailo
add a person with the name Nedelchev, Ivailo
 

Другие публикации лиц с тем же именем

POLAR: placement based on novel rough legalization and refinement., , , , и . ICCAD, стр. 357-362. IEEE, (2013)Log-structured Protocols in Delos., , , , , , , , , и 9 other автор(ы). SOSP, стр. 538-552. ACM, (2021)POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (3): 447-459 (2015)On Timing Closure: Buffer Insertion for Hold-Violation Removal., , , , и . DAC, стр. 6:1-6:6. ACM, (2014)Basic building blocks for asynchronous packet routers., и . Great Lakes Symposium on VLSI, стр. 184-187. IEEE, (1994)Power Compiler: A Gate-Level Power Optimization and Synthesis System., и . ICCD, стр. 74-79. IEEE Computer Society, (1997)Low-latency asynchronous FIFO buffers., , , и . ASYNC, стр. 24-31. IEEE Computer Society, (1995)Asynchronous VLSI design.. University of Surrey, Guildford, UK, (1995)British Library, EThOS.Asynchronous packet routers., и . Interconnection Networks and Mapping and Scheduling Parallel Computations, том 21 из DIMACS Series in Discrete Mathematics and Theoretical Computer Science, стр. 211-227. DIMACS/AMS, (1994)