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Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators.

, , , , , , и . ISQED, стр. 60-66. IEEE, (2021)

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Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , и . CoRR, (2020)A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim., , , , , и . ISPASS, стр. 58-68. IEEE, (2020)SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training., , , , , , , и . HPCA, стр. 58-70. IEEE, (2020)Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI., , , , , , , , , и 2 other автор(ы). ISPASS, стр. 268-279. IEEE, (2024)AIrchitect: Automating Hardware Architecture and Mapping Optimization., , и . DATE, стр. 1-6. IEEE, (2023)RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU., , , , , , и . DAC, стр. 253-258. IEEE, (2021)Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML., , , и . DAC, стр. 583-588. ACM, (2022)Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems., , , и . FPL, стр. 342-349. IEEE, (2019)CLAN: Continuous Learning using Asynchronous Neuroevolution on Commodity Edge Devices., , и . ISPASS, стр. 93-103. IEEE, (2020)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , и . ISQED, стр. 60-66. IEEE, (2021)