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Другие публикации лиц с тем же именем

Reducing Memory Latency via Read-after-Read Memory Dependence Prediction., и . IEEE Trans. Computers, 51 (3): 313-326 (2002)Dynamic Stripes: Exploiting the Dynamic Precision Requirements of Activation Values in Neural Networks., , , и . CoRR, (2017)A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy., и . IEEE Comput. Archit. Lett., 6 (2): 33-36 (2007)Behavior and Performance of Interactive Multi-Player Game Servers., , и . Clust. Comput., 6 (4): 355-366 (2003)Optimizing Memory Translation Emulation in Full System Emulators., , , и . ACM Trans. Archit. Code Optim., 11 (4): 60:1-60:24 (2014)A physical level study and optimization of CAM-based checkpointed register alias table., , и . ISLPED, стр. 233-236. ACM, (2008)On the latency, energy and area of checkpointed, superscalar register alias tables., , , , и . ISLPED, стр. 379-382. ACM, (2007)Reducing OLTP instruction misses with thread migration., , , и . DaMoN, стр. 9-15. ACM, (2012)SPREX: A soft processor with Runahead execution., и . ReConFig, стр. 1-7. IEEE, (2012)A dual grain hit-miss detector for large die-stacked DRAM caches., , , , , и . DATE, стр. 89-92. EDA Consortium San Jose, CA, USA / ACM DL, (2013)