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Two-Graph Approach to Temperature Dependent Skew Scheduling.. ISQED, стр. 432-437. IEEE, (2020)Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 90-A (3): 659-669 (2007)Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis., , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (4): 819-826 (2002)ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits., и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (3): 600-609 (2024)Post-silicon skew tuning algorithm utilizing setup and hold timing tests., и . ISCAS, стр. 125-128. IEEE, (2012)Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis., и . ISQED, стр. 778-783. IEEE, (2012)Optimal register assignment with minimum-delay compensation for latch-based design., и . APCCAS, стр. 887-890. IEEE, (2010)Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis., и . ISCAS, стр. 49-52. IEEE, (2015)Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: extended abstract.. ACM Great Lakes Symposium on VLSI, стр. 91-92. ACM, (2014)A feasibility study on robust programmable delay element design based on neuron-MOS mechanism., и . ACM Great Lakes Symposium on VLSI, стр. 21-26. ACM, (2014)