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Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors., , , и . HPCA, стр. 424-434. IEEE, (2020)An Energy-Efficient Processor Architecture for Embedded Systems., , , , и . IEEE Comput. Archit. Lett., 7 (1): 29-32 (2008)StatTask: reuse distance analysis for task-based applications., , и . RAPIDO@HiPEAC, стр. 1:1-1:7. ACM, (2015)Every walk's a hit: making page walks single-access cache hits., , , и . ASPLOS, стр. 128-141. ACM, (2022)TaskInsight: Understanding Task Schedules Effects on Memory and Performance., , , и . PMAM@PPoPP, стр. 11-20. ACM, (2017)Register pointer architecture for efficient embedded processors., , , , , и . DATE, стр. 600-605. EDA Consortium, San Jose, CA, USA, (2007)Modeling and optimizing NUMA effects and prefetching with machine learning., , , , , и . ICS, стр. 34:1-34:13. ACM, (2020)Understanding the interplay between task scheduling, memory and performance., , и . SPLASH (Companion Volume), стр. 21-23. ACM, (2017)Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit., , , и . J. Signal Process. Syst., 91 (3-4): 379-397 (2019)Dynamically Disabling Way-prediction to Reduce Instruction Replay., , и . ICCD, стр. 140-143. IEEE Computer Society, (2018)