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Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology.

, , , , , , и . IRPS, стр. 1-5. IEEE, (2019)

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Suthinee Bhuvanath

Thangaraj Selvaraj Bhuvaneish

Bharat Balasubramanian

Bharat Kurana

Bharat Kalra

 

Другие публикации лиц с тем же именем

Terrestrial SER characterization for nanoscale technologies: A comparative study., , , , , , , , , и 5 other автор(ы). IRPS, стр. 4. IEEE, (2015)Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology., , , , , , и . IRPS, стр. 1-5. IEEE, (2019)High-Current State triggered by Operating-Frequency Change., , , , , , и . IRPS, стр. 1-4. IEEE, (2020)Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages., , , , и . IRPS, стр. 1-5. IEEE, (2024)Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs., , , , , , , , , и . IRPS, стр. 2. IEEE, (2015)Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node., , , , , и . IRPS, стр. 1-5. IEEE, (2021)Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology., , , , , и . IRPS, стр. 1-5. IEEE, (2021)Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology., , , , , , , и . IRPS, стр. 1. IEEE, (2018)Single-event effects on optical transceiver., , , , и . IRPS, стр. 6-1. IEEE, (2018)Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET., , , , , , , и . IRPS, стр. 10. IEEE, (2024)