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Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores.

, , , , , , , и . ISVLSI, стр. 200-205. IEEE Computer Socity, (2013)

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Vijay Venkateswaran

Sujatha Nagarajan

Vijayasarathi Nagarajan

Venkateswaran Ganesh

Jayendran Venkateswaran

 

Другие публикации лиц с тем же именем

Custom Built Heterogeneous Multi-core Architectures (CUBEMACH): Breaking the conventions., , , , , и . IPDPS Workshops, стр. 1-15. IEEE, (2010)Performance and energy efficient cache system design: Simultaneous execution of multiple applications on heterogeneous cores., , , , , , , и . ISVLSI, стр. 200-205. IEEE Computer Socity, (2013)SCOC IP Cores for Custom Built Supercomputing Nodes., , , , , , , , , и 3 other автор(ы). ISVLSI, стр. 255-260. IEEE Computer Society, (2012)Compilation Accelerator on Silicon., , , , , , , , , и 3 other автор(ы). ISVLSI, стр. 267-272. IEEE Computer Society, (2012)DNA Based Evolutionary Approach for Microprocessor Design Automation., , и . ICANNGA (1), том 4431 из Lecture Notes in Computer Science, стр. 11-22. Springer, (2007)Design for Testability of Functional Cores in High Performance Node Architectures., , и . DELTA, стр. 302-307. IEEE Computer Society, (2008)Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance., , и . IPDPS, IEEE Computer Society, (2005)A Non-Uniform Grid Based Ground Plane Model for High Performance Nodes: The Impact of Heterogeneous Cores on Ground Voltage Gradient., , , и . ISVLSI, стр. 49-54. IEEE Computer Society, (2009)PASCOM: Power Model for Supercomputers., , и . ARCS, том 3894 из Lecture Notes in Computer Science, стр. 326-340. Springer, (2006)Memory in processor: a novel design paradigm for supercomputing architectures., , , , и . SIGARCH Comput. Archit. News, 32 (3): 19-26 (2004)