From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Cases for Analog Mixed Signal Computing Integrated Circuits for Deep Neural Networks., , , , и . VLSI-DAT, стр. 1-2. IEEE, (2019)Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS., , , , и . ISLPED, стр. 140-145. IEEE, (2015)A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity With All Parameters Stored On-Chip., , , и . ESSCIRC, стр. 119-122. IEEE, (2019)A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware., , , , , , , и . J. Signal Process. Syst., 90 (5): 727-741 (2018)An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access., и . IEEE J. Solid State Circuits, 56 (3): 803-813 (2021)In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5ps resolution time-to-digital converter., , , , , , и . ISSCC, стр. 188-189. IEEE, (2010)Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access., и . CICC, стр. 1-4. IEEE, (2020)An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays., , , и . DATE, стр. 1019-1024. IEEE, (2020)A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC., , , , , , и . IEEE J. Solid State Circuits, 44 (10): 2755-2765 (2009)C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism., , , и . IEEE J. Solid State Circuits, 55 (7): 1888-1897 (2020)